Analysis & Synthesis report for testbed
Sat Mar 28 13:38:29 2009
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. General Register Statistics
  8. Inverted Register Statistics
  9. Multiplexer Restructuring Statistics (Restructuring Performed)
 10. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sat Mar 28 13:38:29 2009    ;
; Quartus II Version                 ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name                      ; testbed                                  ;
; Top-level Entity Name              ; TESTBENCH_segment_decoder                ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 512                                      ;
;     Total combinational functions  ; 512                                      ;
;     Dedicated logic registers      ; 96                                       ;
; Total registers                    ; 96                                       ;
; Total pins                         ; 67                                       ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 0                                        ;
; Embedded Multiplier 9-bit elements ; 0                                        ;
; Total PLLs                         ; 0                                        ;
+------------------------------------+------------------------------------------+


+---------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                 ;
+--------------------------------------------------------------+---------------------------+--------------------+
; Option                                                       ; Setting                   ; Default Value      ;
+--------------------------------------------------------------+---------------------------+--------------------+
; Device                                                       ; EP2C20F256C6              ;                    ;
; Top-level entity name                                        ; TESTBENCH_segment_decoder ; testbed            ;
; Family name                                                  ; Cyclone II                ; Stratix II         ;
; Use Generated Physical Constraints File                      ; Off                       ;                    ;
; Use smart compilation                                        ; Off                       ; Off                ;
; Maximum processors allowed for parallel compilation          ; 1                         ; 1                  ;
; Restructure Multiplexers                                     ; Auto                      ; Auto               ;
; Create Debugging Nodes for IP Cores                          ; Off                       ; Off                ;
; Preserve fewer node names                                    ; On                        ; On                 ;
; Disable OpenCore Plus hardware evaluation                    ; Off                       ; Off                ;
; Verilog Version                                              ; Verilog_2001              ; Verilog_2001       ;
; VHDL Version                                                 ; VHDL93                    ; VHDL93             ;
; State Machine Processing                                     ; Auto                      ; Auto               ;
; Safe State Machine                                           ; Off                       ; Off                ;
; Extract Verilog State Machines                               ; On                        ; On                 ;
; Extract VHDL State Machines                                  ; On                        ; On                 ;
; Ignore Verilog initial constructs                            ; Off                       ; Off                ;
; Iteration limit for constant Verilog loops                   ; 5000                      ; 5000               ;
; Iteration limit for non-constant Verilog loops               ; 250                       ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                      ; On                        ; On                 ;
; Parallel Synthesis                                           ; Off                       ; Off                ;
; DSP Block Balancing                                          ; Auto                      ; Auto               ;
; NOT Gate Push-Back                                           ; On                        ; On                 ;
; Power-Up Don't Care                                          ; On                        ; On                 ;
; Remove Redundant Logic Cells                                 ; Off                       ; Off                ;
; Remove Duplicate Registers                                   ; On                        ; On                 ;
; Ignore CARRY Buffers                                         ; Off                       ; Off                ;
; Ignore CASCADE Buffers                                       ; Off                       ; Off                ;
; Ignore GLOBAL Buffers                                        ; Off                       ; Off                ;
; Ignore ROW GLOBAL Buffers                                    ; Off                       ; Off                ;
; Ignore LCELL Buffers                                         ; Off                       ; Off                ;
; Ignore SOFT Buffers                                          ; On                        ; On                 ;
; Limit AHDL Integers to 32 Bits                               ; Off                       ; Off                ;
; Optimization Technique                                       ; Balanced                  ; Balanced           ;
; Carry Chain Length                                           ; 70                        ; 70                 ;
; Auto Carry Chains                                            ; On                        ; On                 ;
; Auto Open-Drain Pins                                         ; On                        ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                        ; Off                       ; Off                ;
; Perform gate-level register retiming                         ; Off                       ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax       ; On                        ; On                 ;
; Auto ROM Replacement                                         ; On                        ; On                 ;
; Auto RAM Replacement                                         ; On                        ; On                 ;
; Auto Shift Register Replacement                              ; Auto                      ; Auto               ;
; Auto Clock Enable Replacement                                ; On                        ; On                 ;
; Strict RAM Replacement                                       ; Off                       ; Off                ;
; Allow Synchronous Control Signals                            ; On                        ; On                 ;
; Force Use of Synchronous Clear Signals                       ; Off                       ; Off                ;
; Auto RAM to Logic Cell Conversion                            ; Off                       ; Off                ;
; Auto Resource Sharing                                        ; Off                       ; Off                ;
; Allow Any RAM Size For Recognition                           ; Off                       ; Off                ;
; Allow Any ROM Size For Recognition                           ; Off                       ; Off                ;
; Allow Any Shift Register Size For Recognition                ; Off                       ; Off                ;
; Ignore translate_off and synthesis_off directives            ; Off                       ; Off                ;
; Show Parameter Settings Tables in Synthesis Report           ; On                        ; On                 ;
; Ignore Maximum Fan-Out Assignments                           ; Off                       ; Off                ;
; Synchronization Register Chain Length                        ; 2                         ; 2                  ;
; PowerPlay Power Optimization                                 ; Normal compilation        ; Normal compilation ;
; HDL message level                                            ; Level2                    ; Level2             ;
; Suppress Register Optimization Related Messages              ; Off                       ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                       ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                       ; 100                ;
; Clock MUX Protection                                         ; On                        ; On                 ;
; Block Design Naming                                          ; Auto                      ; Auto               ;
; SDC constraint protection                                    ; Off                       ; Off                ;
; Synthesis Effort                                             ; Auto                      ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                        ; On                 ;
+--------------------------------------------------------------+---------------------------+--------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                   ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                                                      ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------+
; ../vhdl/SEGMENT_DECODER.vhd      ; yes             ; User VHDL File  ; G:/zeben/school/ECSE487 COMP ARC LAB/project/vhdl/SEGMENT_DECODER.vhd             ;
; TESTBENCH_segment_decoder.vhd    ; yes             ; User VHDL File  ; G:/zeben/school/ECSE487 COMP ARC LAB/project/Altera/TESTBENCH_segment_decoder.vhd ;
+----------------------------------+-----------------+-----------------+-----------------------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 512   ;
;                                             ;       ;
; Total combinational functions               ; 512   ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 384   ;
;     -- 3 input functions                    ; 41    ;
;     -- <=2 input functions                  ; 87    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 474   ;
;     -- arithmetic mode                      ; 38    ;
;                                             ;       ;
; Total registers                             ; 96    ;
;     -- Dedicated logic registers            ; 96    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 67    ;
; Maximum fan-out node                        ; Clock ;
; Maximum fan-out                             ; 96    ;
; Total fan-out                               ; 2209  ;
; Average fan-out                             ; 3.27  ;
+---------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                ;
+---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------+--------------+
; Compilation Hierarchy Node      ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                   ; Library Name ;
+---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------+--------------+
; |TESTBENCH_segment_decoder      ; 512 (143)         ; 96 (96)      ; 0           ; 0            ; 0       ; 0         ; 67   ; 0            ; |TESTBENCH_segment_decoder                            ; work         ;
;    |SEGMENT_DECODER:LED_Driver| ; 369 (369)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |TESTBENCH_segment_decoder|SEGMENT_DECODER:LED_Driver ; work         ;
+---------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 96    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 6     ;
; Number of registers using Asynchronous Clear ; 64    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 46    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+---------------------------------------------------+
; Inverted Register Statistics                      ;
+-----------------------------------------+---------+
; Inverted Register                       ; Fan out ;
+-----------------------------------------+---------+
; A0[5]                                   ; 18      ;
; A0[0]                                   ; 23      ;
; A0[6]                                   ; 15      ;
; A1[5]                                   ; 17      ;
; A1[0]                                   ; 22      ;
; A1[6]                                   ; 14      ;
; A2[5]                                   ; 17      ;
; A2[0]                                   ; 22      ;
; A2[6]                                   ; 14      ;
; A3[5]                                   ; 17      ;
; A3[0]                                   ; 22      ;
; A3[6]                                   ; 14      ;
; A4[5]                                   ; 17      ;
; A4[0]                                   ; 22      ;
; A4[6]                                   ; 14      ;
; A5[5]                                   ; 17      ;
; A5[0]                                   ; 22      ;
; A5[6]                                   ; 14      ;
; A6[5]                                   ; 16      ;
; A6[0]                                   ; 22      ;
; A6[6]                                   ; 14      ;
; A7[5]                                   ; 16      ;
; A7[0]                                   ; 22      ;
; A7[6]                                   ; 14      ;
; counter[0]                              ; 3       ;
; counter[31]                             ; 4       ;
; Total number of inverted registers = 26 ;         ;
+-----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output             ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+
; 3:1                ; 30 bits   ; 60 LEs        ; 30 LEs               ; 30 LEs                 ; Yes        ; |TESTBENCH_segment_decoder|counter[29] ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A0[4]       ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A1[3]       ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A2[2]       ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A3[7]       ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A4[7]       ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A5[4]       ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A6[1]       ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A7[4]       ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|counter[0]  ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A0[5]       ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A1[6]       ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A2[5]       ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A3[0]       ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A4[5]       ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A5[0]       ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A6[6]       ;
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |TESTBENCH_segment_decoder|A7[0]       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Sat Mar 28 13:38:16 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off testbed -c testbed
Warning: Ignored assignments for entity "TESTBENCH_segment_decoder" -- entity does not exist in design
    Warning: Assignment of entity set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" is ignored
    Warning: Assignment of entity set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" is ignored
    Warning: Assignment of entity set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_COLOR 14622752 -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS ON -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PIN_ASSIGNMENTS ON -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS ON -section_id Top is ignored
    Warning: Assignment of entity set_global_assignment -name PARTITION_TYPE STANDARD_PARTITION -section_id Top is ignored
Info: Found 2 design units, including 1 entities, in source file ../vhdl/SEGMENT_DECODER.vhd
    Info: Found design unit 1: SEGMENT_DECODER-thisStuff
    Info: Found entity 1: SEGMENT_DECODER
Info: Found 2 design units, including 1 entities, in source file ../vhdl/encrypt_stage.vhd
    Info: Found design unit 1: encrypt_stage-implementation
    Info: Found entity 1: encrypt_stage
Info: Found 2 design units, including 1 entities, in source file ../vhdl/Permuted_Choice1.vhd
    Info: Found design unit 1: PERMUTED_CHOICE1-logic
    Info: Found entity 1: PERMUTED_CHOICE1
Info: Found 2 design units, including 1 entities, in source file ../vhdl/Permuted_Choice2.vhd
    Info: Found design unit 1: PERMUTED_CHOICE2-logic
    Info: Found entity 1: PERMUTED_CHOICE2
Info: Found 2 design units, including 1 entities, in source file ../vhdl/ShiftLeftBy1.vhd
    Info: Found design unit 1: ShiftLeftBy1-logic
    Info: Found entity 1: ShiftLeftBy1
Info: Found 2 design units, including 1 entities, in source file ../vhdl/ShiftLeftBy2.vhd
    Info: Found design unit 1: ShiftLeftBy2-logic
    Info: Found entity 1: ShiftLeftBy2
Info: Found 2 design units, including 1 entities, in source file ../vhdl/cipher_function.vhd
    Info: Found design unit 1: cipher_function-implementation
    Info: Found entity 1: cipher_function
Info: Found 2 design units, including 1 entities, in source file ../vhdl/ShiftRightBy1.vhd
    Info: Found design unit 1: ShiftRightBy1-logic
    Info: Found entity 1: ShiftRightBy1
Info: Found 2 design units, including 1 entities, in source file ../vhdl/ShiftRightBy2.vhd
    Info: Found design unit 1: ShiftRightBy2-logic
    Info: Found entity 1: ShiftRightBy2
Info: Found 2 design units, including 1 entities, in source file ../vhdl/initial_permutation.vhd
    Info: Found design unit 1: initial_permutation-logic
    Info: Found entity 1: initial_permutation
Info: Found 2 design units, including 1 entities, in source file ../vhdl/inverse_permutation.vhd
    Info: Found design unit 1: inverse_permutation-logic
    Info: Found entity 1: inverse_permutation
Info: Found 2 design units, including 1 entities, in source file ../vhdl/pipe_reg.vhd
    Info: Found design unit 1: pipe_reg-implementation
    Info: Found entity 1: pipe_reg
Info: Found 2 design units, including 1 entities, in source file ../vhdl/Shift_Register.vhd
    Info: Found design unit 1: Shift_Register-logic
    Info: Found entity 1: Shift_Register
Info: Found 2 design units, including 1 entities, in source file ../vhdl/Inverse_Key_Scheduler.vhd
    Info: Found design unit 1: Inverse_Key_Scheduler-logic
    Info: Found entity 1: Inverse_Key_Scheduler
Info: Found 2 design units, including 1 entities, in source file ../vhdl/DECRYPTER_SYSTEM.vhd
    Info: Found design unit 1: DECRYPTER_SYSTEM-logic
    Info: Found entity 1: DECRYPTER_SYSTEM
Info: Found 2 design units, including 1 entities, in source file ../vhdl/lookup.vhd
    Info: Found design unit 1: lookup-LUT
    Info: Found entity 1: lookup
Info: Found 2 design units, including 1 entities, in source file ../vhdl/keygen.vhd
    Info: Found design unit 1: keygen-singleKey
    Info: Found entity 1: keygen
Info: Found 2 design units, including 1 entities, in source file ../vhdl/Key_Scheduler.vhd
    Info: Found design unit 1: Key_Scheduler-logic
    Info: Found entity 1: Key_Scheduler
Info: Found 2 design units, including 1 entities, in source file ../vhdl/ENCRYPTER_SYSTEM.vhd
    Info: Found design unit 1: ENCRYPTER_SYSTEM-implementation
    Info: Found entity 1: ENCRYPTER_SYSTEM
Info: Found 2 design units, including 1 entities, in source file ../vhdl/TESTBED.vhd
    Info: Found design unit 1: TESTBED-logic
    Info: Found entity 1: TESTBED
Info: Found 2 design units, including 1 entities, in source file TESTBENCH_segment_decoder.vhd
    Info: Found design unit 1: TESTBENCH_segment_decoder-singleKey
    Info: Found entity 1: TESTBENCH_segment_decoder
Info: Elaborating entity "TESTBENCH_segment_decoder" for the top level hierarchy
Info: Elaborating entity "SEGMENT_DECODER" for hierarchy "SEGMENT_DECODER:LED_Driver"
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 613 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 64 output pins
    Info: Implemented 546 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings
    Info: Peak virtual memory: 181 megabytes
    Info: Processing ended: Sat Mar 28 13:38:29 2009
    Info: Elapsed time: 00:00:13
    Info: Total CPU time (on all processors): 00:00:13


