Analysis & Synthesis report for CPLD430
Wed Nov 04 13:01:34 2009
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |CPLD430|PS2Interface:ps2|key_fsm
  8. User-Specified and Inferred Latches
  9. Analysis & Synthesis Equations
 10. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
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functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
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without limitation, that your use is for the sole purpose of   
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Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Nov 04 13:01:34 2009    ;
; Quartus II Version          ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name               ; CPLD430                                  ;
; Top-level Entity Name       ; CPLD430                                  ;
; Family                      ; MAX7000AE                                ;
; Total macrocells            ; 98                                       ;
; Total pins                  ; 63                                       ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                          ;
+----------------------------------------------------------------------+-----------------+---------------+
; Option                                                               ; Setting         ; Default Value ;
+----------------------------------------------------------------------+-----------------+---------------+
; Device                                                               ; EPM7128AELC84-7 ;               ;
; Top-level entity name                                                ; CPLD430         ; CPLD430       ;
; Family name                                                          ; MAX7000AE       ; Stratix       ;
; Optimization Technique -- MAX 7000B/7000AE/3000A/7000S/7000A         ; Area            ; Speed         ;
; Use smart compilation                                                ; Off             ; Off           ;
; Create Debugging Nodes for IP Cores                                  ; off             ; off           ;
; Preserve fewer node names                                            ; On              ; On            ;
; Disable OpenCore Plus hardware evaluation                            ; Off             ; Off           ;
; Verilog Version                                                      ; Verilog_2001    ; Verilog_2001  ;
; VHDL Version                                                         ; VHDL93          ; VHDL93        ;
; State Machine Processing                                             ; Auto            ; Auto          ;
; Extract Verilog State Machines                                       ; On              ; On            ;
; Extract VHDL State Machines                                          ; On              ; On            ;
; Add Pass-Through Logic to Inferred RAMs                              ; On              ; On            ;
; NOT Gate Push-Back                                                   ; On              ; On            ;
; Power-Up Don't Care                                                  ; On              ; On            ;
; Remove Redundant Logic Cells                                         ; Off             ; Off           ;
; Remove Duplicate Registers                                           ; On              ; On            ;
; Ignore CARRY Buffers                                                 ; Off             ; Off           ;
; Ignore CASCADE Buffers                                               ; Off             ; Off           ;
; Ignore GLOBAL Buffers                                                ; Off             ; Off           ;
; Ignore ROW GLOBAL Buffers                                            ; Off             ; Off           ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A           ; Auto            ; Auto          ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A            ; Off             ; Off           ;
; Limit AHDL Integers to 32 Bits                                       ; Off             ; Off           ;
; Allow XOR Gate Usage                                                 ; On              ; On            ;
; Auto Logic Cell Insertion                                            ; On              ; On            ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4               ; 4             ;
; Auto Parallel Expanders                                              ; On              ; On            ;
; Auto Open-Drain Pins                                                 ; On              ; On            ;
; Remove Duplicate Logic                                               ; On              ; On            ;
; Auto Resource Sharing                                                ; Off             ; Off           ;
; Maximum Fan-in Per Macrocell -- MAX 7000B/7000AE/3000A/7000S/7000A   ; 100             ; 100           ;
; Ignore translate_off and translate_on Synthesis Directives           ; Off             ; Off           ;
; Show Parameter Settings Tables in Synthesis Report                   ; On              ; On            ;
+----------------------------------------------------------------------+-----------------+---------------+


+------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                               ;
+----------------------------------+-----------------+-----------------+-------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path  ;
+----------------------------------+-----------------+-----------------+-------------------------------+
; PS2Interface.vhd                 ; yes             ; User VHDL File  ; C:/temp/CPLD/PS2Interface.vhd ;
; CPLD430.vhd                      ; yes             ; User VHDL File  ; C:/temp/CPLD/CPLD430.vhd      ;
+----------------------------------+-----------------+-----------------+-------------------------------+


+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------+----------------------+
; Resource             ; Usage                ;
+----------------------+----------------------+
; Logic cells          ; 98                   ;
; Total registers      ; 70                   ;
; I/O pins             ; 63                   ;
; Shareable expanders  ; 3                    ;
; Maximum fan-out node ; ps2_clk~19           ;
; Maximum fan-out      ; 40                   ;
; Total fan-out        ; 466                  ;
; Average fan-out      ; 2.84                 ;
+----------------------+----------------------+


+----------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                        ;
+----------------------------+------------+------+---------------------------+
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name       ;
+----------------------------+------------+------+---------------------------+
; |CPLD430                   ; 98         ; 63   ; |CPLD430                  ;
;    |PS2Interface:ps2|      ; 41         ; 0    ; |CPLD430|PS2Interface:ps2 ;
+----------------------------+------------+------+---------------------------+


+---------------------------------------------------+
; State Machine - |CPLD430|PS2Interface:ps2|key_fsm ;
+---------------------+------------+----------------+
; Name                ; key_fsm~20 ; key_fsm~19     ;
+---------------------+------------+----------------+
; key_fsm.start       ; 0          ; 0              ;
; key_fsm.receive_bit ; 1          ; 1              ;
; key_fsm.parity      ; 0          ; 1              ;
; key_fsm.stop        ; 1          ; 0              ;
+---------------------+------------+----------------+


+---------------------------------------------------+
; User-Specified and Inferred Latches               ;
+-----------------------------------------------+---+
; Latch Name                                    ;   ;
+-----------------------------------------------+---+
; ps2_clk                                       ;   ;
; spi_transmit[0]                               ;   ;
; Number of user-specified and inferred latches ; 2 ;
+-----------------------------------------------+---+
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in C:/temp/CPLD/CPLD430.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Wed Nov 04 13:01:33 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CPLD430 -c CPLD430
Info: Found 2 design units, including 1 entities, in source file PS2Interface.vhd
    Info: Found design unit 1: PS2Interface-arch
    Info: Found entity 1: PS2Interface
Info: Found 2 design units, including 1 entities, in source file CPLD430.vhd
    Info: Found design unit 1: CPLD430-arch1
    Info: Found entity 1: CPLD430
Info: Elaborating entity "CPLD430" for the top level hierarchy
Warning: VHDL Process Statement warning at CPLD430.vhd(189): signal or variable "spi_transmit" may not be assigned a new value in every possible path through the Process Statement. Signal or variable "spi_transmit" holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Warning: Output port "OUTB_0" at CPLD430.vhd(67) has no driver
Warning: Output port "OUTB_1" at CPLD430.vhd(68) has no driver
Warning: Output port "OUTB_2" at CPLD430.vhd(69) has no driver
Warning: Output port "OUTB_3" at CPLD430.vhd(70) has no driver
Warning: Output port "OUTB_4" at CPLD430.vhd(71) has no driver
Warning: Output port "OUTB_5" at CPLD430.vhd(72) has no driver
Warning: Output port "OUTB_6" at CPLD430.vhd(73) has no driver
Warning: Output port "OUTC_1" at CPLD430.vhd(79) has no driver
Warning: Output port "OUTC_2" at CPLD430.vhd(80) has no driver
Warning: Output port "OUTC_3" at CPLD430.vhd(81) has no driver
Warning: Output port "OUTC_4" at CPLD430.vhd(82) has no driver
Warning: Output port "OUTC_5" at CPLD430.vhd(83) has no driver
Warning: Output port "OUTC_6" at CPLD430.vhd(84) has no driver
Info: Elaborating entity "PS2Interface" for hierarchy "PS2Interface:ps2"
Info: State machine "|CPLD430|PS2Interface:ps2|key_fsm" contains 4 states and 0 state bits
Info: Selected Auto state machine encoding method for state machine "|CPLD430|PS2Interface:ps2|key_fsm"
Info: Encoding result for state machine "|CPLD430|PS2Interface:ps2|key_fsm"
    Info: Completed encoding using 2 state bits
        Info: Encoded state bit "PS2Interface:ps2|key_fsm~20"
        Info: Encoded state bit "PS2Interface:ps2|key_fsm~19"
    Info: State "|CPLD430|PS2Interface:ps2|key_fsm.start" uses code string "00"
    Info: State "|CPLD430|PS2Interface:ps2|key_fsm.receive_bit" uses code string "11"
    Info: State "|CPLD430|PS2Interface:ps2|key_fsm.parity" uses code string "01"
    Info: State "|CPLD430|PS2Interface:ps2|key_fsm.stop" uses code string "10"
Info: Duplicate registers merged to single register
    Info: Duplicate register "PS2Interface:ps2|data_bytes[10]" merged to single register "PS2Interface:ps2|data_bytes[11]"
    Info: Duplicate register "PS2Interface:ps2|data_bytes[9]" merged to single register "PS2Interface:ps2|data_bytes[11]"
    Info: Duplicate register "PS2Interface:ps2|data_bytes[8]" merged to single register "PS2Interface:ps2|data_bytes[11]"
    Info: Duplicate register "PS2Interface:ps2|scancode[10]" merged to single register "PS2Interface:ps2|scancode[11]"
    Info: Duplicate register "PS2Interface:ps2|scancode[9]" merged to single register "PS2Interface:ps2|scancode[11]"
    Info: Duplicate register "PS2Interface:ps2|scancode[8]" merged to single register "PS2Interface:ps2|scancode[11]"
    Info: Duplicate register "PS2Interface:ps2|data_bytes[18]" merged to single register "PS2Interface:ps2|data_bytes[19]"
    Info: Duplicate register "PS2Interface:ps2|data_bytes[17]" merged to single register "PS2Interface:ps2|data_bytes[19]"
    Info: Duplicate register "PS2Interface:ps2|data_bytes[16]" merged to single register "PS2Interface:ps2|data_bytes[19]"
    Info: Duplicate register "PS2Interface:ps2|scancode[19]" merged to single register "PS2Interface:ps2|scancode[17]"
    Info: Duplicate register "PS2Interface:ps2|scancode[18]" merged to single register "PS2Interface:ps2|scancode[17]"
    Info: Duplicate register "PS2Interface:ps2|scancode[16]" merged to single register "PS2Interface:ps2|scancode[17]"
Warning: Reduced register "PS2Interface:ps2|data_bytes[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "PS2Interface:ps2|scancode[11]" with stuck data_in port to stuck value GND
Warning: Reduced register "PS2Interface:ps2|data_bytes[19]" with stuck data_in port to stuck value GND
Warning: Reduced register "PS2Interface:ps2|scancode[17]" with stuck data_in port to stuck value GND
Warning: Output pins are stuck at VCC or GND
    Warning: Pin "OUTB_0" stuck at GND
    Warning: Pin "OUTB_1" stuck at GND
    Warning: Pin "OUTB_2" stuck at GND
    Warning: Pin "OUTB_3" stuck at GND
    Warning: Pin "OUTB_4" stuck at GND
    Warning: Pin "OUTB_5" stuck at GND
    Warning: Pin "OUTB_6" stuck at GND
    Warning: Pin "OUTC_1" stuck at GND
    Warning: Pin "OUTC_2" stuck at GND
    Warning: Pin "OUTC_3" stuck at GND
    Warning: Pin "OUTC_4" stuck at GND
    Warning: Pin "OUTC_5" stuck at GND
    Warning: Pin "OUTC_6" stuck at GND
    Warning: Pin "CLK_en" stuck at VCC
Warning: Design contains 28 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "PORT1_0"
    Warning: No output dependent on input pin "PORT1_1"
    Warning: No output dependent on input pin "PORT1_2"
    Warning: No output dependent on input pin "PORT1_3"
    Warning: No output dependent on input pin "PORT1_4"
    Warning: No output dependent on input pin "PORT1_5"
    Warning: No output dependent on input pin "PORT1_6"
    Warning: No output dependent on input pin "PORT1_7"
    Warning: No output dependent on input pin "PORT2_1"
    Warning: No output dependent on input pin "PORT2_2"
    Warning: No output dependent on input pin "PORT2_3"
    Warning: No output dependent on input pin "PORT2_4"
    Warning: No output dependent on input pin "PORT2_5"
    Warning: No output dependent on input pin "PORT2_6"
    Warning: No output dependent on input pin "PORT2_7"
    Warning: No output dependent on input pin "PORT4_0"
    Warning: No output dependent on input pin "PORT4_1"
    Warning: No output dependent on input pin "PORT4_2"
    Warning: No output dependent on input pin "PORT4_3"
    Warning: No output dependent on input pin "PORT4_4"
    Warning: No output dependent on input pin "PORT4_5"
    Warning: No output dependent on input pin "PORT4_6"
    Warning: No output dependent on input pin "PORT4_7"
    Warning: No output dependent on input pin "PORT5_4"
    Warning: No output dependent on input pin "PORT5_5"
    Warning: No output dependent on input pin "CLK"
    Warning: No output dependent on input pin "GLB_RSTn"
    Warning: No output dependent on input pin "OE"
Info: Implemented 164 device resources after synthesis - the final resource count might be different
    Info: Implemented 36 input pins
    Info: Implemented 27 output pins
    Info: Implemented 98 macrocells
    Info: Implemented 3 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 62 warnings
    Info: Processing ended: Wed Nov 04 13:01:34 2009
    Info: Elapsed time: 00:00:38


