Analysis & Synthesis report for g07_Nth_Root
Tue Nov 18 15:27:42 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. Analysis & Synthesis DSP Block Usage Summary
  8. State Machine - |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state
  9. General Register Statistics
 10. Inverted Register Statistics
 11. Multiplexer Restructuring Statistics (Restructuring Performed)
 12. Parameter Settings for Inferred Entity Instance: g07_Nth_Root:G0|lpm_mult:Mult0
 13. Parameter Settings for Inferred Entity Instance: g07_Nth_Root:G0|lpm_mult:Mult1
 14. Parameter Settings for Inferred Entity Instance: g07_Nth_Root:G0|lpm_mult:Mult2
 15. lpm_mult Parameter Settings by Entity Instance
 16. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                  ;
+------------------------------------+------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Tue Nov 18 15:27:42 2008    ;
; Quartus II Version                 ; 8.0 Build 215 05/29/2008 SJ Full Version ;
; Revision Name                      ; g07_Nth_Root                             ;
; Top-level Entity Name              ; g07_Nth_Root_TESTBED                     ;
; Family                             ; Cyclone II                               ;
; Total logic elements               ; 552                                      ;
;     Total combinational functions  ; 552                                      ;
;     Dedicated logic registers      ; 123                                      ;
; Total registers                    ; 123                                      ;
; Total pins                         ; 45                                       ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 0                                        ;
; Embedded Multiplier 9-bit elements ; 7                                        ;
; Total PLLs                         ; 0                                        ;
+------------------------------------+------------------------------------------+


+----------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                            ;
+--------------------------------------------------------------+----------------------+--------------------+
; Option                                                       ; Setting              ; Default Value      ;
+--------------------------------------------------------------+----------------------+--------------------+
; Device                                                       ; EP2C20F484C7         ;                    ;
; Top-level entity name                                        ; g07_Nth_Root_TESTBED ; g07_Nth_Root       ;
; Family name                                                  ; Cyclone II           ; Stratix II         ;
; Use Generated Physical Constraints File                      ; Off                  ;                    ;
; Use smart compilation                                        ; Off                  ; Off                ;
; Maximum processors allowed for parallel compilation          ; 1                    ; 1                  ;
; Restructure Multiplexers                                     ; Auto                 ; Auto               ;
; Create Debugging Nodes for IP Cores                          ; Off                  ; Off                ;
; Preserve fewer node names                                    ; On                   ; On                 ;
; Disable OpenCore Plus hardware evaluation                    ; Off                  ; Off                ;
; Verilog Version                                              ; Verilog_2001         ; Verilog_2001       ;
; VHDL Version                                                 ; VHDL93               ; VHDL93             ;
; State Machine Processing                                     ; Auto                 ; Auto               ;
; Safe State Machine                                           ; Off                  ; Off                ;
; Extract Verilog State Machines                               ; On                   ; On                 ;
; Extract VHDL State Machines                                  ; On                   ; On                 ;
; Ignore Verilog initial constructs                            ; Off                  ; Off                ;
; Iteration limit for constant Verilog loops                   ; 5000                 ; 5000               ;
; Iteration limit for non-constant Verilog loops               ; 250                  ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                      ; On                   ; On                 ;
; Parallel Synthesis                                           ; Off                  ; Off                ;
; DSP Block Balancing                                          ; Auto                 ; Auto               ;
; NOT Gate Push-Back                                           ; On                   ; On                 ;
; Power-Up Don't Care                                          ; On                   ; On                 ;
; Remove Redundant Logic Cells                                 ; Off                  ; Off                ;
; Remove Duplicate Registers                                   ; On                   ; On                 ;
; Ignore CARRY Buffers                                         ; Off                  ; Off                ;
; Ignore CASCADE Buffers                                       ; Off                  ; Off                ;
; Ignore GLOBAL Buffers                                        ; Off                  ; Off                ;
; Ignore ROW GLOBAL Buffers                                    ; Off                  ; Off                ;
; Ignore LCELL Buffers                                         ; Off                  ; Off                ;
; Ignore SOFT Buffers                                          ; On                   ; On                 ;
; Limit AHDL Integers to 32 Bits                               ; Off                  ; Off                ;
; Optimization Technique                                       ; Balanced             ; Balanced           ;
; Carry Chain Length                                           ; 70                   ; 70                 ;
; Auto Carry Chains                                            ; On                   ; On                 ;
; Auto Open-Drain Pins                                         ; On                   ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                        ; Off                  ; Off                ;
; Perform gate-level register retiming                         ; Off                  ; Off                ;
; Allow register retiming to trade off Tsu/Tco with Fmax       ; On                   ; On                 ;
; Auto ROM Replacement                                         ; On                   ; On                 ;
; Auto RAM Replacement                                         ; On                   ; On                 ;
; Auto Shift Register Replacement                              ; Auto                 ; Auto               ;
; Auto Clock Enable Replacement                                ; On                   ; On                 ;
; Strict RAM Replacement                                       ; Off                  ; Off                ;
; Allow Synchronous Control Signals                            ; On                   ; On                 ;
; Force Use of Synchronous Clear Signals                       ; Off                  ; Off                ;
; Auto RAM to Logic Cell Conversion                            ; Off                  ; Off                ;
; Auto Resource Sharing                                        ; Off                  ; Off                ;
; Allow Any RAM Size For Recognition                           ; Off                  ; Off                ;
; Allow Any ROM Size For Recognition                           ; Off                  ; Off                ;
; Allow Any Shift Register Size For Recognition                ; Off                  ; Off                ;
; Ignore translate_off and synthesis_off directives            ; Off                  ; Off                ;
; Show Parameter Settings Tables in Synthesis Report           ; On                   ; On                 ;
; Ignore Maximum Fan-Out Assignments                           ; Off                  ; Off                ;
; Synchronization Register Chain Length                        ; 2                    ; 2                  ;
; PowerPlay Power Optimization                                 ; Normal compilation   ; Normal compilation ;
; HDL message level                                            ; Level2               ; Level2             ;
; Suppress Register Optimization Related Messages              ; Off                  ; Off                ;
; Number of Removed Registers Reported in Synthesis Report     ; 100                  ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report    ; 100                  ; 100                ;
; Clock MUX Protection                                         ; On                   ; On                 ;
; Block Design Naming                                          ; Auto                 ; Auto               ;
; SDC constraint protection                                    ; Off                  ; Off                ;
; Synthesis Effort                                             ; Auto                 ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On                   ; On                 ;
+--------------------------------------------------------------+----------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                    ;
+---------------------------------------------------+-----------------+------------------------------+----------------------------------------------------------------------+
; File Name with User-Entered Path                  ; Used in Netlist ; File Type                    ; File Name with Absolute Path                                         ;
+---------------------------------------------------+-----------------+------------------------------+----------------------------------------------------------------------+
; Segment Decoder from lab2/g07_segment_decoder.vhd ; yes             ; User VHDL File               ; S:/DSD_LAB4/Part2/Segment Decoder from lab2/g07_segment_decoder.vhd  ;
; g07_Nth_Root.vhd                                  ; yes             ; User VHDL File               ; S:/DSD_LAB4/Part2/g07_Nth_Root.vhd                                   ;
; TESTBED/g07_Nth_Root_TESTBED.vhd                  ; yes             ; User VHDL File               ; S:/DSD_LAB4/Part2/TESTBED/g07_Nth_Root_TESTBED.vhd                   ;
; lpm_mult.tdf                                      ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/lpm_mult.tdf            ;
; aglobal80.inc                                     ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/aglobal80.inc           ;
; lpm_add_sub.inc                                   ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/lpm_add_sub.inc         ;
; multcore.inc                                      ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/multcore.inc            ;
; bypassff.inc                                      ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/bypassff.inc            ;
; altshift.inc                                      ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/altshift.inc            ;
; multcore.tdf                                      ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/multcore.tdf            ;
; csa_add.inc                                       ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/csa_add.inc             ;
; mpar_add.inc                                      ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/mpar_add.inc            ;
; muleabz.inc                                       ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/muleabz.inc             ;
; mul_lfrg.inc                                      ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/mul_lfrg.inc            ;
; mul_boothc.inc                                    ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/mul_boothc.inc          ;
; alt_ded_mult.inc                                  ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/alt_ded_mult.inc        ;
; alt_ded_mult_y.inc                                ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/alt_ded_mult_y.inc      ;
; dffpipe.inc                                       ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/dffpipe.inc             ;
; mpar_add.tdf                                      ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/mpar_add.tdf            ;
; lpm_add_sub.tdf                                   ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/lpm_add_sub.tdf         ;
; addcore.inc                                       ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/addcore.inc             ;
; look_add.inc                                      ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/look_add.inc            ;
; alt_stratix_add_sub.inc                           ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/alt_stratix_add_sub.inc ;
; alt_mercury_add_sub.inc                           ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/alt_mercury_add_sub.inc ;
; db/add_sub_2ch.tdf                                ; yes             ; Auto-Generated Megafunction  ; S:/DSD_LAB4/Part2/db/add_sub_2ch.tdf                                 ;
; db/add_sub_6ch.tdf                                ; yes             ; Auto-Generated Megafunction  ; S:/DSD_LAB4/Part2/db/add_sub_6ch.tdf                                 ;
; altshift.tdf                                      ; yes             ; Megafunction                 ; c:/altera/80/quartus/libraries/megafunctions/altshift.tdf            ;
; db/mult_1v01.tdf                                  ; yes             ; Auto-Generated Megafunction  ; S:/DSD_LAB4/Part2/db/mult_1v01.tdf                                   ;
+---------------------------------------------------+-----------------+------------------------------+----------------------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 552   ;
;                                             ;       ;
; Total combinational functions               ; 552   ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 351   ;
;     -- 3 input functions                    ; 145   ;
;     -- <=2 input functions                  ; 56    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 461   ;
;     -- arithmetic mode                      ; 91    ;
;                                             ;       ;
; Total registers                             ; 123   ;
;     -- Dedicated logic registers            ; 123   ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 45    ;
; Embedded Multiplier 9-bit elements          ; 7     ;
; Maximum fan-out node                        ; CLOCK ;
; Maximum fan-out                             ; 123   ;
; Total fan-out                               ; 2459  ;
; Average fan-out                             ; 3.38  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                         ;
+---------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                        ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                                          ; Library Name ;
+---------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
; |g07_Nth_Root_TESTBED                             ; 552 (5)           ; 123 (15)     ; 0           ; 7            ; 1       ; 3         ; 45   ; 0            ; |g07_Nth_Root_TESTBED                                                                                                                                        ; work         ;
;    |g07_Nth_Root:G0|                              ; 286 (175)         ; 108 (108)    ; 0           ; 7            ; 1       ; 3         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0                                                                                                                        ; work         ;
;       |lpm_mult:Mult0|                            ; 45 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult0                                                                                                         ; work         ;
;          |multcore:mult_core|                     ; 45 (18)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult0|multcore:mult_core                                                                                      ; work         ;
;             |mpar_add:padder|                     ; 27 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder                                                                      ; work         ;
;                |lpm_add_sub:adder[0]|             ; 9 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                 ; work         ;
;                   |add_sub_2ch:auto_generated|    ; 9 (9)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_2ch:auto_generated                      ; work         ;
;                |lpm_add_sub:adder[1]|             ; 7 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]                                                 ; work         ;
;                   |add_sub_2ch:auto_generated|    ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]|add_sub_2ch:auto_generated                      ; work         ;
;                |mpar_add:sub_par_add|             ; 11 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add                                                 ; work         ;
;                   |lpm_add_sub:adder[0]|          ; 11 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]                            ; work         ;
;                      |add_sub_6ch:auto_generated| ; 11 (11)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]|add_sub_6ch:auto_generated ; work         ;
;       |lpm_mult:Mult1|                            ; 20 (0)            ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult1                                                                                                         ; work         ;
;          |multcore:mult_core|                     ; 20 (12)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult1|multcore:mult_core                                                                                      ; work         ;
;             |mpar_add:padder|                     ; 8 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder                                                                      ; work         ;
;                |lpm_add_sub:adder[0]|             ; 8 (0)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]                                                 ; work         ;
;                   |add_sub_2ch:auto_generated|    ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|add_sub_2ch:auto_generated                      ; work         ;
;       |lpm_mult:Mult2|                            ; 46 (0)            ; 0 (0)        ; 0           ; 7            ; 1       ; 3         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult2                                                                                                         ; work         ;
;          |mult_1v01:auto_generated|               ; 46 (46)           ; 0 (0)        ; 0           ; 7            ; 1       ; 3         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|lpm_mult:Mult2|mult_1v01:auto_generated                                                                                ; work         ;
;    |g07_segment_decoder:G1|                       ; 91 (91)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_segment_decoder:G1                                                                                                                 ; work         ;
;    |g07_segment_decoder:G2|                       ; 82 (82)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_segment_decoder:G2                                                                                                                 ; work         ;
;    |g07_segment_decoder:G4|                       ; 88 (88)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |g07_Nth_Root_TESTBED|g07_segment_decoder:G4                                                                                                                 ; work         ;
+---------------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+-----------------------------------------------------+
; Analysis & Synthesis DSP Block Usage Summary        ;
+---------------------------------------+-------------+
; Statistic                             ; Number Used ;
+---------------------------------------+-------------+
; Simple Multipliers (9-bit)            ; 1           ;
; Simple Multipliers (18-bit)           ; 3           ;
; Embedded Multiplier Blocks            ; --          ;
; Embedded Multiplier 9-bit elements    ; 7           ;
; Signed Embedded Multipliers           ; 0           ;
; Unsigned Embedded Multipliers         ; 4           ;
; Mixed Sign Embedded Multipliers       ; 0           ;
; Variable Sign Embedded Multipliers    ; 0           ;
; Dedicated Input Shift Register Chains ; 0           ;
+---------------------------------------+-------------+
Note: number of Embedded Multiplier Blocks used is only available after a successful fit.


Encoding Type:  One-Hot
+--------------------------------------------------------------------------------------------------------------------------+
; State Machine - |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state                                                              ;
+-----------+-----------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
; Name      ; state.s99 ; state.s8 ; state.s7 ; state.s6 ; state.s5 ; state.s4 ; state.s3 ; state.s2 ; state.s1 ; state.s0 ;
+-----------+-----------+----------+----------+----------+----------+----------+----------+----------+----------+----------+
; state.s0  ; 0         ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ;
; state.s1  ; 0         ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ; 1        ;
; state.s2  ; 0         ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ; 0        ; 1        ;
; state.s3  ; 0         ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ; 0        ; 0        ; 1        ;
; state.s4  ; 0         ; 0        ; 0        ; 0        ; 0        ; 1        ; 0        ; 0        ; 0        ; 1        ;
; state.s5  ; 0         ; 0        ; 0        ; 0        ; 1        ; 0        ; 0        ; 0        ; 0        ; 1        ;
; state.s6  ; 0         ; 0        ; 0        ; 1        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ;
; state.s7  ; 0         ; 0        ; 1        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ;
; state.s8  ; 0         ; 1        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ;
; state.s99 ; 1         ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 0        ; 1        ;
+-----------+-----------+----------+----------+----------+----------+----------+----------+----------+----------+----------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 123   ;
; Number of registers using Synchronous Clear  ; 21    ;
; Number of registers using Synchronous Load   ; 6     ;
; Number of registers using Asynchronous Clear ; 32    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 91    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; g07_Nth_Root:G0|BC[4]                  ; 5       ;
; g07_Nth_Root:G0|BC[0]                  ; 18      ;
; g07_Nth_Root:G0|BC[1]                  ; 18      ;
; g07_Nth_Root:G0|BC[2]                  ; 17      ;
; g07_Nth_Root:G0|BC[3]                  ; 18      ;
; g07_Nth_Root:G0|BC[5]                  ; 4       ;
; Total number of inverted registers = 6 ;         ;
+----------------------------------------+---------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                  ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------+
; 5:1                ; 6 bits    ; 18 LEs        ; 6 LEs                ; 12 LEs                 ; Yes        ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|N_TEMP[0]   ;
; 6:1                ; 21 bits   ; 84 LEs        ; 42 LEs               ; 42 LEs                 ; Yes        ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|Z[25]       ;
; 7:1                ; 21 bits   ; 84 LEs        ; 21 LEs               ; 63 LEs                 ; Yes        ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|Z[2]        ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|BC[4]       ;
; 128:1              ; 2 bits    ; 170 LEs       ; 100 LEs              ; 70 LEs                 ; No         ; |g07_Nth_Root_TESTBED|g07_segment_decoder:G2|a[6] ;
; 128:1              ; 2 bits    ; 170 LEs       ; 100 LEs              ; 70 LEs                 ; No         ; |g07_Nth_Root_TESTBED|g07_segment_decoder:G1|a[6] ;
; 128:1              ; 2 bits    ; 170 LEs       ; 100 LEs              ; 70 LEs                 ; No         ; |g07_Nth_Root_TESTBED|g07_segment_decoder:G4|a[4] ;
; 8:1                ; 2 bits    ; 10 LEs        ; 6 LEs                ; 4 LEs                  ; No         ; |g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state~32    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+---------------------------------------------------+


+-----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: g07_Nth_Root:G0|lpm_mult:Mult0   ;
+------------------------------------------------+------------+---------------------+
; Parameter Name                                 ; Value      ; Type                ;
+------------------------------------------------+------------+---------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY          ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY        ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE        ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE      ;
; LPM_WIDTHA                                     ; 14         ; Untyped             ;
; LPM_WIDTHB                                     ; 7          ; Untyped             ;
; LPM_WIDTHP                                     ; 21         ; Untyped             ;
; LPM_WIDTHR                                     ; 21         ; Untyped             ;
; LPM_WIDTHS                                     ; 1          ; Untyped             ;
; LPM_REPRESENTATION                             ; UNSIGNED   ; Untyped             ;
; LPM_PIPELINE                                   ; 0          ; Untyped             ;
; LATENCY                                        ; 0          ; Untyped             ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped             ;
; INPUT_B_IS_CONSTANT                            ; YES        ; Untyped             ;
; USE_EAB                                        ; OFF        ; Untyped             ;
; MAXIMIZE_SPEED                                 ; 5          ; Untyped             ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped             ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped             ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO       ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped             ;
; CBXI_PARAMETER                                 ; NOTHING    ; Untyped             ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped             ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped             ;
; USE_AHDL_IMPLEMENTATION                        ; OFF        ; Untyped             ;
+------------------------------------------------+------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: g07_Nth_Root:G0|lpm_mult:Mult1   ;
+------------------------------------------------+------------+---------------------+
; Parameter Name                                 ; Value      ; Type                ;
+------------------------------------------------+------------+---------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY          ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY        ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE        ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE      ;
; LPM_WIDTHA                                     ; 7          ; Untyped             ;
; LPM_WIDTHB                                     ; 7          ; Untyped             ;
; LPM_WIDTHP                                     ; 14         ; Untyped             ;
; LPM_WIDTHR                                     ; 14         ; Untyped             ;
; LPM_WIDTHS                                     ; 1          ; Untyped             ;
; LPM_REPRESENTATION                             ; UNSIGNED   ; Untyped             ;
; LPM_PIPELINE                                   ; 0          ; Untyped             ;
; LATENCY                                        ; 0          ; Untyped             ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped             ;
; INPUT_B_IS_CONSTANT                            ; YES        ; Untyped             ;
; USE_EAB                                        ; OFF        ; Untyped             ;
; MAXIMIZE_SPEED                                 ; 5          ; Untyped             ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped             ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped             ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO       ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped             ;
; CBXI_PARAMETER                                 ; NOTHING    ; Untyped             ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped             ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped             ;
; USE_AHDL_IMPLEMENTATION                        ; OFF        ; Untyped             ;
+------------------------------------------------+------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: g07_Nth_Root:G0|lpm_mult:Mult2   ;
+------------------------------------------------+------------+---------------------+
; Parameter Name                                 ; Value      ; Type                ;
+------------------------------------------------+------------+---------------------+
; AUTO_CARRY_CHAINS                              ; ON         ; AUTO_CARRY          ;
; IGNORE_CARRY_BUFFERS                           ; OFF        ; IGNORE_CARRY        ;
; AUTO_CASCADE_CHAINS                            ; ON         ; AUTO_CASCADE        ;
; IGNORE_CASCADE_BUFFERS                         ; OFF        ; IGNORE_CASCADE      ;
; LPM_WIDTHA                                     ; 21         ; Untyped             ;
; LPM_WIDTHB                                     ; 21         ; Untyped             ;
; LPM_WIDTHP                                     ; 42         ; Untyped             ;
; LPM_WIDTHR                                     ; 42         ; Untyped             ;
; LPM_WIDTHS                                     ; 1          ; Untyped             ;
; LPM_REPRESENTATION                             ; UNSIGNED   ; Untyped             ;
; LPM_PIPELINE                                   ; 0          ; Untyped             ;
; LATENCY                                        ; 0          ; Untyped             ;
; INPUT_A_IS_CONSTANT                            ; NO         ; Untyped             ;
; INPUT_B_IS_CONSTANT                            ; NO         ; Untyped             ;
; USE_EAB                                        ; OFF        ; Untyped             ;
; MAXIMIZE_SPEED                                 ; 5          ; Untyped             ;
; DEVICE_FAMILY                                  ; Cyclone II ; Untyped             ;
; CARRY_CHAIN                                    ; MANUAL     ; Untyped             ;
; APEX20K_TECHNOLOGY_MAPPER                      ; LUT        ; TECH_MAPPER_APEX20K ;
; DEDICATED_MULTIPLIER_CIRCUITRY                 ; AUTO       ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_INPUT_WIDTH_FOR_AUTO  ; 0          ; Untyped             ;
; DEDICATED_MULTIPLIER_MIN_OUTPUT_WIDTH_FOR_AUTO ; 0          ; Untyped             ;
; CBXI_PARAMETER                                 ; mult_1v01  ; Untyped             ;
; INPUT_A_FIXED_VALUE                            ; Bx         ; Untyped             ;
; INPUT_B_FIXED_VALUE                            ; Bx         ; Untyped             ;
; USE_AHDL_IMPLEMENTATION                        ; OFF        ; Untyped             ;
+------------------------------------------------+------------+---------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; lpm_mult Parameter Settings by Entity Instance                         ;
+---------------------------------------+--------------------------------+
; Name                                  ; Value                          ;
+---------------------------------------+--------------------------------+
; Number of entity instances            ; 3                              ;
; Entity Instance                       ; g07_Nth_Root:G0|lpm_mult:Mult0 ;
;     -- LPM_WIDTHA                     ; 14                             ;
;     -- LPM_WIDTHB                     ; 7                              ;
;     -- LPM_WIDTHP                     ; 21                             ;
;     -- LPM_REPRESENTATION             ; UNSIGNED                       ;
;     -- INPUT_A_IS_CONSTANT            ; NO                             ;
;     -- INPUT_B_IS_CONSTANT            ; YES                            ;
;     -- USE_EAB                        ; OFF                            ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                           ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                             ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                             ;
; Entity Instance                       ; g07_Nth_Root:G0|lpm_mult:Mult1 ;
;     -- LPM_WIDTHA                     ; 7                              ;
;     -- LPM_WIDTHB                     ; 7                              ;
;     -- LPM_WIDTHP                     ; 14                             ;
;     -- LPM_REPRESENTATION             ; UNSIGNED                       ;
;     -- INPUT_A_IS_CONSTANT            ; NO                             ;
;     -- INPUT_B_IS_CONSTANT            ; YES                            ;
;     -- USE_EAB                        ; OFF                            ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                           ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                             ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                             ;
; Entity Instance                       ; g07_Nth_Root:G0|lpm_mult:Mult2 ;
;     -- LPM_WIDTHA                     ; 21                             ;
;     -- LPM_WIDTHB                     ; 21                             ;
;     -- LPM_WIDTHP                     ; 42                             ;
;     -- LPM_REPRESENTATION             ; UNSIGNED                       ;
;     -- INPUT_A_IS_CONSTANT            ; NO                             ;
;     -- INPUT_B_IS_CONSTANT            ; NO                             ;
;     -- USE_EAB                        ; OFF                            ;
;     -- DEDICATED_MULTIPLIER_CIRCUITRY ; AUTO                           ;
;     -- INPUT_A_FIXED_VALUE            ; Bx                             ;
;     -- INPUT_B_FIXED_VALUE            ; Bx                             ;
+---------------------------------------+--------------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Tue Nov 18 15:27:27 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off g07_Nth_Root -c g07_Nth_Root
Info: Found 2 design units, including 1 entities, in source file Segment Decoder from lab2/g07_segment_decoder.vhd
    Info: Found design unit 1: g07_segment_decoder-decoder
    Info: Found entity 1: g07_segment_decoder
Info: Found 2 design units, including 1 entities, in source file g07_Nth_Root.vhd
    Info: Found design unit 1: g07_Nth_Root-logic
    Info: Found entity 1: g07_Nth_Root
Info: Found 2 design units, including 1 entities, in source file TESTBED/g07_Nth_Root_TESTBED.vhd
    Info: Found design unit 1: g07_Nth_Root_TESTBED-loading
    Info: Found entity 1: g07_Nth_Root_TESTBED
Info: Elaborating entity "g07_Nth_Root_TESTBED" for the top level hierarchy
Warning (10036): Verilog HDL or VHDL warning at g07_Nth_Root_TESTBED.vhd(53): object "d2" assigned a value but never read
Warning (10036): Verilog HDL or VHDL warning at g07_Nth_Root_TESTBED.vhd(54): object "rbo" assigned a value but never read
Info: Elaborating entity "g07_Nth_Root" for hierarchy "g07_Nth_Root:G0"
Info: Elaborating entity "g07_segment_decoder" for hierarchy "g07_segment_decoder:G1"
Info: State machine "|g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state" contains 10 states
Info: Selected Auto state machine encoding method for state machine "|g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state"
Info: Encoding result for state machine "|g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state"
    Info: Completed encoding using 10 state bits
        Info: Encoded state bit "g07_Nth_Root:G0|state.s99"
        Info: Encoded state bit "g07_Nth_Root:G0|state.s8"
        Info: Encoded state bit "g07_Nth_Root:G0|state.s7"
        Info: Encoded state bit "g07_Nth_Root:G0|state.s6"
        Info: Encoded state bit "g07_Nth_Root:G0|state.s5"
        Info: Encoded state bit "g07_Nth_Root:G0|state.s4"
        Info: Encoded state bit "g07_Nth_Root:G0|state.s3"
        Info: Encoded state bit "g07_Nth_Root:G0|state.s2"
        Info: Encoded state bit "g07_Nth_Root:G0|state.s1"
        Info: Encoded state bit "g07_Nth_Root:G0|state.s0"
    Info: State "|g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state.s0" uses code string "0000000000"
    Info: State "|g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state.s1" uses code string "0000000011"
    Info: State "|g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state.s2" uses code string "0000000101"
    Info: State "|g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state.s3" uses code string "0000001001"
    Info: State "|g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state.s4" uses code string "0000010001"
    Info: State "|g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state.s5" uses code string "0000100001"
    Info: State "|g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state.s6" uses code string "0001000001"
    Info: State "|g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state.s7" uses code string "0010000001"
    Info: State "|g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state.s8" uses code string "0100000001"
    Info: State "|g07_Nth_Root_TESTBED|g07_Nth_Root:G0|state.s99" uses code string "1000000001"
Info: Inferred 3 megafunctions from design logic
    Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "g07_Nth_Root:G0|Mult0"
    Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "g07_Nth_Root:G0|Mult1"
    Info: Inferred multiplier megafunction ("lpm_mult") from the following logic: "g07_Nth_Root:G0|Mult2"
Info: Elaborated megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult0"
Info: Instantiated megafunction "g07_Nth_Root:G0|lpm_mult:Mult0" with the following parameter:
    Info: Parameter "LPM_WIDTHA" = "14"
    Info: Parameter "LPM_WIDTHB" = "7"
    Info: Parameter "LPM_WIDTHP" = "21"
    Info: Parameter "LPM_WIDTHR" = "21"
    Info: Parameter "LPM_WIDTHS" = "1"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "INPUT_A_IS_CONSTANT" = "NO"
    Info: Parameter "INPUT_B_IS_CONSTANT" = "YES"
    Info: Parameter "MAXIMIZE_SPEED" = "5"
    Info: Parameter "DEDICATED_MULTIPLIER_CIRCUITRY" = "AUTO"
Info: Elaborated megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult0|multcore:mult_core", which is child of megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult0"
Info: Elaborated megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult0"
Info: Elaborated megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[1]", which is child of megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult0"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_2ch.tdf
    Info: Found entity 1: add_sub_2ch
Info: Elaborated megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add", which is child of megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult0"
Info: Elaborated megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult0|multcore:mult_core|mpar_add:padder|mpar_add:sub_par_add|lpm_add_sub:adder[0]", which is child of megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult0"
Info: Found 1 design units, including 1 entities, in source file db/add_sub_6ch.tdf
    Info: Found entity 1: add_sub_6ch
Info: Elaborated megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult0|altshift:external_latency_ffs", which is child of megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult0"
Info: Elaborated megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult1"
Info: Instantiated megafunction "g07_Nth_Root:G0|lpm_mult:Mult1" with the following parameter:
    Info: Parameter "LPM_WIDTHA" = "7"
    Info: Parameter "LPM_WIDTHB" = "7"
    Info: Parameter "LPM_WIDTHP" = "14"
    Info: Parameter "LPM_WIDTHR" = "14"
    Info: Parameter "LPM_WIDTHS" = "1"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "INPUT_A_IS_CONSTANT" = "NO"
    Info: Parameter "INPUT_B_IS_CONSTANT" = "YES"
    Info: Parameter "MAXIMIZE_SPEED" = "5"
    Info: Parameter "DEDICATED_MULTIPLIER_CIRCUITRY" = "AUTO"
Info: Elaborated megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult1|multcore:mult_core", which is child of megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult1"
Info: Elaborated megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult1|multcore:mult_core|mpar_add:padder", which is child of megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult1"
Info: Elaborated megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult1|altshift:external_latency_ffs", which is child of megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult1"
Info: Elaborated megafunction instantiation "g07_Nth_Root:G0|lpm_mult:Mult2"
Info: Instantiated megafunction "g07_Nth_Root:G0|lpm_mult:Mult2" with the following parameter:
    Info: Parameter "LPM_WIDTHA" = "21"
    Info: Parameter "LPM_WIDTHB" = "21"
    Info: Parameter "LPM_WIDTHP" = "42"
    Info: Parameter "LPM_WIDTHR" = "42"
    Info: Parameter "LPM_WIDTHS" = "1"
    Info: Parameter "LPM_REPRESENTATION" = "UNSIGNED"
    Info: Parameter "INPUT_A_IS_CONSTANT" = "NO"
    Info: Parameter "INPUT_B_IS_CONSTANT" = "NO"
    Info: Parameter "MAXIMIZE_SPEED" = "5"
    Info: Parameter "DEDICATED_MULTIPLIER_CIRCUITRY" = "AUTO"
Info: Found 1 design units, including 1 entities, in source file db/mult_1v01.tdf
    Info: Found entity 1: mult_1v01
Info: Ignored 134 buffer(s)
    Info: Ignored 134 SOFT buffer(s)
Warning: Output pins are stuck at VCC or GND
    Warning (13410): Pin "hex2[0]" is stuck at VCC
    Warning (13410): Pin "hex2[1]" is stuck at VCC
    Warning (13410): Pin "hex2[2]" is stuck at VCC
    Warning (13410): Pin "hex2[3]" is stuck at VCC
    Warning (13410): Pin "hex2[4]" is stuck at VCC
    Warning (13410): Pin "hex2[5]" is stuck at VCC
    Warning (13410): Pin "hex2[6]" is stuck at VCC
Warning: Design contains 2 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "sw[7]"
    Warning (15610): No output dependent on input pin "key[2]"
Info: Implemented 654 device resources after synthesis - the final resource count might be different
    Info: Implemented 15 input pins
    Info: Implemented 30 output pins
    Info: Implemented 602 logic cells
    Info: Implemented 7 DSP elements
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 13 warnings
    Info: Peak virtual memory: 187 megabytes
    Info: Processing ended: Tue Nov 18 15:27:43 2008
    Info: Elapsed time: 00:00:16
    Info: Total CPU time (on all processors): 00:00:12


