Simulator report for G07_Full_adder
Tue Sep 23 14:06:07 2008
Quartus II Version 8.0 Build 215 05/29/2008 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Simulator Summary
  3. Simulator Settings
  4. Simulation Waveforms
  5. Coverage Summary
  6. Complete 1/0-Value Coverage
  7. Missing 1-Value Coverage
  8. Missing 0-Value Coverage
  9. Simulator INI Usage
 10. Simulator Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+--------------------------------------------+
; Simulator Summary                          ;
+-----------------------------+--------------+
; Type                        ; Value        ;
+-----------------------------+--------------+
; Simulation Start Time       ; 0 ps         ;
; Simulation End Time         ; 6.05 us      ;
; Simulation Netlist Size     ; 222 nodes    ;
; Simulation Coverage         ;      79.73 % ;
; Total Number of Transitions ; 4601         ;
; Simulation Breakpoints      ; 0            ;
; Family                      ; Cyclone II   ;
+-----------------------------+--------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings                                                                                                               ;
+--------------------------------------------------------------------------------------------+---------------------+---------------+
; Option                                                                                     ; Setting             ; Default Value ;
+--------------------------------------------------------------------------------------------+---------------------+---------------+
; Simulation mode                                                                            ; Functional          ; Timing        ;
; Start time                                                                                 ; 0 ns                ; 0 ns          ;
; Simulation results format                                                                  ; CVWF                ;               ;
; Vector input source                                                                        ; /28BitFullAdder.vwf ;               ;
; Add pins automatically to simulation output waveforms                                      ; On                  ; On            ;
; Check outputs                                                                              ; Off                 ; Off           ;
; Report simulation coverage                                                                 ; On                  ; On            ;
; Display complete 1/0 value coverage report                                                 ; On                  ; On            ;
; Display missing 1-value coverage report                                                    ; On                  ; On            ;
; Display missing 0-value coverage report                                                    ; On                  ; On            ;
; Detect setup and hold time violations                                                      ; Off                 ; Off           ;
; Detect glitches                                                                            ; Off                 ; Off           ;
; Disable timing delays in Timing Simulation                                                 ; Off                 ; Off           ;
; Generate Signal Activity File                                                              ; Off                 ; Off           ;
; Generate VCD File for PowerPlay Power Analyzer                                             ; Off                 ; Off           ;
; Group bus channels in simulation results                                                   ; Off                 ; Off           ;
; Preserve fewer signal transitions to reduce memory requirements                            ; On                  ; On            ;
; Trigger vector comparison with the specified mode                                          ; INPUT_EDGE          ; INPUT_EDGE    ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off                 ; Off           ;
; Overwrite Waveform Inputs With Simulation Outputs                                          ; On                  ;               ;
; Perform Glitch Filtering in Timing Simulation                                              ; Auto                ; Auto          ;
+--------------------------------------------------------------------------------------------+---------------------+---------------+


+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.


+--------------------------------------------------------------------+
; Coverage Summary                                                   ;
+-----------------------------------------------------+--------------+
; Type                                                ; Value        ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage                      ;      79.73 % ;
; Total nodes checked                                 ; 222          ;
; Total output ports checked                          ; 222          ;
; Total output ports with complete 1/0-value coverage ; 177          ;
; Total output ports with no 1/0-value coverage       ; 44           ;
; Total output ports with no 1-value coverage         ; 44           ;
; Total output ports with no 0-value coverage         ; 45           ;
+-----------------------------------------------------+--------------+


The following table displays output ports that toggle between 1 and 0 during simulation.
+--------------------------------------------------------------------------------------------------------------+
; Complete 1/0-Value Coverage                                                                                  ;
+---------------------------------------------+---------------------------------------------+------------------+
; Node Name                                   ; Output Port Name                            ; Output Port Type ;
+---------------------------------------------+---------------------------------------------+------------------+
; |G07_28BitAdder|C_out_29                    ; |G07_28BitAdder|C_out_29                    ; pin_out          ;
; |G07_28BitAdder|A[27]                       ; |G07_28BitAdder|A[27]                       ; out              ;
; |G07_28BitAdder|A[26]                       ; |G07_28BitAdder|A[26]                       ; out              ;
; |G07_28BitAdder|A[25]                       ; |G07_28BitAdder|A[25]                       ; out              ;
; |G07_28BitAdder|A[24]                       ; |G07_28BitAdder|A[24]                       ; out              ;
; |G07_28BitAdder|A[23]                       ; |G07_28BitAdder|A[23]                       ; out              ;
; |G07_28BitAdder|A[22]                       ; |G07_28BitAdder|A[22]                       ; out              ;
; |G07_28BitAdder|A[21]                       ; |G07_28BitAdder|A[21]                       ; out              ;
; |G07_28BitAdder|A[20]                       ; |G07_28BitAdder|A[20]                       ; out              ;
; |G07_28BitAdder|A[19]                       ; |G07_28BitAdder|A[19]                       ; out              ;
; |G07_28BitAdder|A[18]                       ; |G07_28BitAdder|A[18]                       ; out              ;
; |G07_28BitAdder|A[17]                       ; |G07_28BitAdder|A[17]                       ; out              ;
; |G07_28BitAdder|A[16]                       ; |G07_28BitAdder|A[16]                       ; out              ;
; |G07_28BitAdder|A[15]                       ; |G07_28BitAdder|A[15]                       ; out              ;
; |G07_28BitAdder|A[14]                       ; |G07_28BitAdder|A[14]                       ; out              ;
; |G07_28BitAdder|A[13]                       ; |G07_28BitAdder|A[13]                       ; out              ;
; |G07_28BitAdder|A[12]                       ; |G07_28BitAdder|A[12]                       ; out              ;
; |G07_28BitAdder|A[11]                       ; |G07_28BitAdder|A[11]                       ; out              ;
; |G07_28BitAdder|A[10]                       ; |G07_28BitAdder|A[10]                       ; out              ;
; |G07_28BitAdder|A[9]                        ; |G07_28BitAdder|A[9]                        ; out              ;
; |G07_28BitAdder|A[8]                        ; |G07_28BitAdder|A[8]                        ; out              ;
; |G07_28BitAdder|A[7]                        ; |G07_28BitAdder|A[7]                        ; out              ;
; |G07_28BitAdder|A[6]                        ; |G07_28BitAdder|A[6]                        ; out              ;
; |G07_28BitAdder|A[5]                        ; |G07_28BitAdder|A[5]                        ; out              ;
; |G07_28BitAdder|A[4]                        ; |G07_28BitAdder|A[4]                        ; out              ;
; |G07_28BitAdder|A[3]                        ; |G07_28BitAdder|A[3]                        ; out              ;
; |G07_28BitAdder|A[2]                        ; |G07_28BitAdder|A[2]                        ; out              ;
; |G07_28BitAdder|A[1]                        ; |G07_28BitAdder|A[1]                        ; out              ;
; |G07_28BitAdder|A[0]                        ; |G07_28BitAdder|A[0]                        ; out              ;
; |G07_28BitAdder|B[27]                       ; |G07_28BitAdder|B[27]                       ; out              ;
; |G07_28BitAdder|B[26]                       ; |G07_28BitAdder|B[26]                       ; out              ;
; |G07_28BitAdder|B[25]                       ; |G07_28BitAdder|B[25]                       ; out              ;
; |G07_28BitAdder|B[24]                       ; |G07_28BitAdder|B[24]                       ; out              ;
; |G07_28BitAdder|B[23]                       ; |G07_28BitAdder|B[23]                       ; out              ;
; |G07_28BitAdder|B[22]                       ; |G07_28BitAdder|B[22]                       ; out              ;
; |G07_28BitAdder|B[21]                       ; |G07_28BitAdder|B[21]                       ; out              ;
; |G07_28BitAdder|B[20]                       ; |G07_28BitAdder|B[20]                       ; out              ;
; |G07_28BitAdder|B[19]                       ; |G07_28BitAdder|B[19]                       ; out              ;
; |G07_28BitAdder|B[18]                       ; |G07_28BitAdder|B[18]                       ; out              ;
; |G07_28BitAdder|B[17]                       ; |G07_28BitAdder|B[17]                       ; out              ;
; |G07_28BitAdder|B[16]                       ; |G07_28BitAdder|B[16]                       ; out              ;
; |G07_28BitAdder|B[15]                       ; |G07_28BitAdder|B[15]                       ; out              ;
; |G07_28BitAdder|B[14]                       ; |G07_28BitAdder|B[14]                       ; out              ;
; |G07_28BitAdder|B[13]                       ; |G07_28BitAdder|B[13]                       ; out              ;
; |G07_28BitAdder|B[12]                       ; |G07_28BitAdder|B[12]                       ; out              ;
; |G07_28BitAdder|B[11]                       ; |G07_28BitAdder|B[11]                       ; out              ;
; |G07_28BitAdder|B[10]                       ; |G07_28BitAdder|B[10]                       ; out              ;
; |G07_28BitAdder|B[9]                        ; |G07_28BitAdder|B[9]                        ; out              ;
; |G07_28BitAdder|B[8]                        ; |G07_28BitAdder|B[8]                        ; out              ;
; |G07_28BitAdder|B[7]                        ; |G07_28BitAdder|B[7]                        ; out              ;
; |G07_28BitAdder|B[6]                        ; |G07_28BitAdder|B[6]                        ; out              ;
; |G07_28BitAdder|B[5]                        ; |G07_28BitAdder|B[5]                        ; out              ;
; |G07_28BitAdder|B[4]                        ; |G07_28BitAdder|B[4]                        ; out              ;
; |G07_28BitAdder|B[3]                        ; |G07_28BitAdder|B[3]                        ; out              ;
; |G07_28BitAdder|B[2]                        ; |G07_28BitAdder|B[2]                        ; out              ;
; |G07_28BitAdder|B[1]                        ; |G07_28BitAdder|B[1]                        ; out              ;
; |G07_28BitAdder|B[0]                        ; |G07_28BitAdder|B[0]                        ; out              ;
; |G07_28BitAdder|SUM[27]                     ; |G07_28BitAdder|SUM[27]                     ; pin_out          ;
; |G07_28BitAdder|SUM[26]                     ; |G07_28BitAdder|SUM[26]                     ; pin_out          ;
; |G07_28BitAdder|SUM[25]                     ; |G07_28BitAdder|SUM[25]                     ; pin_out          ;
; |G07_28BitAdder|SUM[24]                     ; |G07_28BitAdder|SUM[24]                     ; pin_out          ;
; |G07_28BitAdder|SUM[23]                     ; |G07_28BitAdder|SUM[23]                     ; pin_out          ;
; |G07_28BitAdder|SUM[22]                     ; |G07_28BitAdder|SUM[22]                     ; pin_out          ;
; |G07_28BitAdder|SUM[21]                     ; |G07_28BitAdder|SUM[21]                     ; pin_out          ;
; |G07_28BitAdder|SUM[20]                     ; |G07_28BitAdder|SUM[20]                     ; pin_out          ;
; |G07_28BitAdder|SUM[19]                     ; |G07_28BitAdder|SUM[19]                     ; pin_out          ;
; |G07_28BitAdder|SUM[18]                     ; |G07_28BitAdder|SUM[18]                     ; pin_out          ;
; |G07_28BitAdder|SUM[17]                     ; |G07_28BitAdder|SUM[17]                     ; pin_out          ;
; |G07_28BitAdder|SUM[16]                     ; |G07_28BitAdder|SUM[16]                     ; pin_out          ;
; |G07_28BitAdder|SUM[15]                     ; |G07_28BitAdder|SUM[15]                     ; pin_out          ;
; |G07_28BitAdder|SUM[14]                     ; |G07_28BitAdder|SUM[14]                     ; pin_out          ;
; |G07_28BitAdder|SUM[13]                     ; |G07_28BitAdder|SUM[13]                     ; pin_out          ;
; |G07_28BitAdder|SUM[12]                     ; |G07_28BitAdder|SUM[12]                     ; pin_out          ;
; |G07_28BitAdder|SUM[11]                     ; |G07_28BitAdder|SUM[11]                     ; pin_out          ;
; |G07_28BitAdder|SUM[10]                     ; |G07_28BitAdder|SUM[10]                     ; pin_out          ;
; |G07_28BitAdder|SUM[9]                      ; |G07_28BitAdder|SUM[9]                      ; pin_out          ;
; |G07_28BitAdder|SUM[8]                      ; |G07_28BitAdder|SUM[8]                      ; pin_out          ;
; |G07_28BitAdder|SUM[7]                      ; |G07_28BitAdder|SUM[7]                      ; pin_out          ;
; |G07_28BitAdder|SUM[6]                      ; |G07_28BitAdder|SUM[6]                      ; pin_out          ;
; |G07_28BitAdder|SUM[5]                      ; |G07_28BitAdder|SUM[5]                      ; pin_out          ;
; |G07_28BitAdder|SUM[4]                      ; |G07_28BitAdder|SUM[4]                      ; pin_out          ;
; |G07_28BitAdder|SUM[3]                      ; |G07_28BitAdder|SUM[3]                      ; pin_out          ;
; |G07_28BitAdder|SUM[2]                      ; |G07_28BitAdder|SUM[2]                      ; pin_out          ;
; |G07_28BitAdder|SUM[1]                      ; |G07_28BitAdder|SUM[1]                      ; pin_out          ;
; |G07_28BitAdder|SUM[0]                      ; |G07_28BitAdder|SUM[0]                      ; pin_out          ;
; |G07_28BitAdder|G07_Full_adder:inst16|inst5 ; |G07_28BitAdder|G07_Full_adder:inst16|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst16|inst  ; |G07_28BitAdder|G07_Full_adder:inst16|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst17|inst4 ; |G07_28BitAdder|G07_Full_adder:inst17|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst17|inst5 ; |G07_28BitAdder|G07_Full_adder:inst17|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst17|inst6 ; |G07_28BitAdder|G07_Full_adder:inst17|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst17|inst  ; |G07_28BitAdder|G07_Full_adder:inst17|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst17|inst1 ; |G07_28BitAdder|G07_Full_adder:inst17|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst18|inst4 ; |G07_28BitAdder|G07_Full_adder:inst18|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst18|inst5 ; |G07_28BitAdder|G07_Full_adder:inst18|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst18|inst6 ; |G07_28BitAdder|G07_Full_adder:inst18|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst18|inst  ; |G07_28BitAdder|G07_Full_adder:inst18|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst19|inst4 ; |G07_28BitAdder|G07_Full_adder:inst19|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst19|inst5 ; |G07_28BitAdder|G07_Full_adder:inst19|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst19|inst6 ; |G07_28BitAdder|G07_Full_adder:inst19|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst19|inst  ; |G07_28BitAdder|G07_Full_adder:inst19|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst20|inst4 ; |G07_28BitAdder|G07_Full_adder:inst20|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst20|inst5 ; |G07_28BitAdder|G07_Full_adder:inst20|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst20|inst6 ; |G07_28BitAdder|G07_Full_adder:inst20|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst20|inst  ; |G07_28BitAdder|G07_Full_adder:inst20|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst21|inst4 ; |G07_28BitAdder|G07_Full_adder:inst21|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst21|inst5 ; |G07_28BitAdder|G07_Full_adder:inst21|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst21|inst6 ; |G07_28BitAdder|G07_Full_adder:inst21|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst21|inst  ; |G07_28BitAdder|G07_Full_adder:inst21|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst22|inst4 ; |G07_28BitAdder|G07_Full_adder:inst22|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst22|inst5 ; |G07_28BitAdder|G07_Full_adder:inst22|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst22|inst6 ; |G07_28BitAdder|G07_Full_adder:inst22|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst22|inst  ; |G07_28BitAdder|G07_Full_adder:inst22|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst23|inst4 ; |G07_28BitAdder|G07_Full_adder:inst23|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst23|inst5 ; |G07_28BitAdder|G07_Full_adder:inst23|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst23|inst6 ; |G07_28BitAdder|G07_Full_adder:inst23|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst23|inst  ; |G07_28BitAdder|G07_Full_adder:inst23|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst24|inst4 ; |G07_28BitAdder|G07_Full_adder:inst24|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst24|inst5 ; |G07_28BitAdder|G07_Full_adder:inst24|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst24|inst6 ; |G07_28BitAdder|G07_Full_adder:inst24|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst24|inst  ; |G07_28BitAdder|G07_Full_adder:inst24|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst25|inst4 ; |G07_28BitAdder|G07_Full_adder:inst25|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst25|inst6 ; |G07_28BitAdder|G07_Full_adder:inst25|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst25|inst  ; |G07_28BitAdder|G07_Full_adder:inst25|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst26|inst4 ; |G07_28BitAdder|G07_Full_adder:inst26|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst26|inst6 ; |G07_28BitAdder|G07_Full_adder:inst26|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst26|inst  ; |G07_28BitAdder|G07_Full_adder:inst26|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst27|inst4 ; |G07_28BitAdder|G07_Full_adder:inst27|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst27|inst6 ; |G07_28BitAdder|G07_Full_adder:inst27|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst27|inst  ; |G07_28BitAdder|G07_Full_adder:inst27|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst28|inst4 ; |G07_28BitAdder|G07_Full_adder:inst28|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst28|inst6 ; |G07_28BitAdder|G07_Full_adder:inst28|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst28|inst  ; |G07_28BitAdder|G07_Full_adder:inst28|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst29|inst4 ; |G07_28BitAdder|G07_Full_adder:inst29|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst29|inst6 ; |G07_28BitAdder|G07_Full_adder:inst29|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst29|inst  ; |G07_28BitAdder|G07_Full_adder:inst29|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst30|inst4 ; |G07_28BitAdder|G07_Full_adder:inst30|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst30|inst6 ; |G07_28BitAdder|G07_Full_adder:inst30|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst30|inst  ; |G07_28BitAdder|G07_Full_adder:inst30|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst31|inst4 ; |G07_28BitAdder|G07_Full_adder:inst31|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst31|inst6 ; |G07_28BitAdder|G07_Full_adder:inst31|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst31|inst  ; |G07_28BitAdder|G07_Full_adder:inst31|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst32|inst4 ; |G07_28BitAdder|G07_Full_adder:inst32|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst32|inst6 ; |G07_28BitAdder|G07_Full_adder:inst32|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst32|inst  ; |G07_28BitAdder|G07_Full_adder:inst32|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst33|inst4 ; |G07_28BitAdder|G07_Full_adder:inst33|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst33|inst6 ; |G07_28BitAdder|G07_Full_adder:inst33|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst33|inst  ; |G07_28BitAdder|G07_Full_adder:inst33|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst34|inst4 ; |G07_28BitAdder|G07_Full_adder:inst34|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst34|inst6 ; |G07_28BitAdder|G07_Full_adder:inst34|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst34|inst  ; |G07_28BitAdder|G07_Full_adder:inst34|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst35|inst4 ; |G07_28BitAdder|G07_Full_adder:inst35|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst35|inst6 ; |G07_28BitAdder|G07_Full_adder:inst35|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst35|inst  ; |G07_28BitAdder|G07_Full_adder:inst35|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst36|inst4 ; |G07_28BitAdder|G07_Full_adder:inst36|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst36|inst6 ; |G07_28BitAdder|G07_Full_adder:inst36|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst36|inst  ; |G07_28BitAdder|G07_Full_adder:inst36|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst37|inst4 ; |G07_28BitAdder|G07_Full_adder:inst37|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst37|inst6 ; |G07_28BitAdder|G07_Full_adder:inst37|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst37|inst  ; |G07_28BitAdder|G07_Full_adder:inst37|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst38|inst4 ; |G07_28BitAdder|G07_Full_adder:inst38|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst38|inst6 ; |G07_28BitAdder|G07_Full_adder:inst38|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst38|inst  ; |G07_28BitAdder|G07_Full_adder:inst38|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst39|inst4 ; |G07_28BitAdder|G07_Full_adder:inst39|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst39|inst6 ; |G07_28BitAdder|G07_Full_adder:inst39|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst39|inst  ; |G07_28BitAdder|G07_Full_adder:inst39|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst40|inst4 ; |G07_28BitAdder|G07_Full_adder:inst40|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst40|inst6 ; |G07_28BitAdder|G07_Full_adder:inst40|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst40|inst  ; |G07_28BitAdder|G07_Full_adder:inst40|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst41|inst4 ; |G07_28BitAdder|G07_Full_adder:inst41|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst41|inst6 ; |G07_28BitAdder|G07_Full_adder:inst41|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst41|inst  ; |G07_28BitAdder|G07_Full_adder:inst41|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst42|inst4 ; |G07_28BitAdder|G07_Full_adder:inst42|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst42|inst6 ; |G07_28BitAdder|G07_Full_adder:inst42|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst42|inst  ; |G07_28BitAdder|G07_Full_adder:inst42|inst  ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst43|inst4 ; |G07_28BitAdder|G07_Full_adder:inst43|inst4 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst43|inst6 ; |G07_28BitAdder|G07_Full_adder:inst43|inst6 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst43|inst  ; |G07_28BitAdder|G07_Full_adder:inst43|inst  ; out0             ;
+---------------------------------------------+---------------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                                     ;
+---------------------------------------------+---------------------------------------------+------------------+
; Node Name                                   ; Output Port Name                            ; Output Port Type ;
+---------------------------------------------+---------------------------------------------+------------------+
; |G07_28BitAdder|G07_Full_adder:inst18|inst1 ; |G07_28BitAdder|G07_Full_adder:inst18|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst19|inst1 ; |G07_28BitAdder|G07_Full_adder:inst19|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst20|inst1 ; |G07_28BitAdder|G07_Full_adder:inst20|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst21|inst1 ; |G07_28BitAdder|G07_Full_adder:inst21|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst22|inst1 ; |G07_28BitAdder|G07_Full_adder:inst22|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst23|inst1 ; |G07_28BitAdder|G07_Full_adder:inst23|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst24|inst1 ; |G07_28BitAdder|G07_Full_adder:inst24|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst25|inst1 ; |G07_28BitAdder|G07_Full_adder:inst25|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst26|inst5 ; |G07_28BitAdder|G07_Full_adder:inst26|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst26|inst1 ; |G07_28BitAdder|G07_Full_adder:inst26|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst27|inst5 ; |G07_28BitAdder|G07_Full_adder:inst27|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst27|inst1 ; |G07_28BitAdder|G07_Full_adder:inst27|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst28|inst5 ; |G07_28BitAdder|G07_Full_adder:inst28|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst28|inst1 ; |G07_28BitAdder|G07_Full_adder:inst28|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst29|inst5 ; |G07_28BitAdder|G07_Full_adder:inst29|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst29|inst1 ; |G07_28BitAdder|G07_Full_adder:inst29|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst30|inst5 ; |G07_28BitAdder|G07_Full_adder:inst30|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst30|inst1 ; |G07_28BitAdder|G07_Full_adder:inst30|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst31|inst5 ; |G07_28BitAdder|G07_Full_adder:inst31|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst31|inst1 ; |G07_28BitAdder|G07_Full_adder:inst31|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst32|inst5 ; |G07_28BitAdder|G07_Full_adder:inst32|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst32|inst1 ; |G07_28BitAdder|G07_Full_adder:inst32|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst33|inst5 ; |G07_28BitAdder|G07_Full_adder:inst33|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst33|inst1 ; |G07_28BitAdder|G07_Full_adder:inst33|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst34|inst5 ; |G07_28BitAdder|G07_Full_adder:inst34|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst34|inst1 ; |G07_28BitAdder|G07_Full_adder:inst34|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst35|inst5 ; |G07_28BitAdder|G07_Full_adder:inst35|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst35|inst1 ; |G07_28BitAdder|G07_Full_adder:inst35|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst36|inst5 ; |G07_28BitAdder|G07_Full_adder:inst36|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst36|inst1 ; |G07_28BitAdder|G07_Full_adder:inst36|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst37|inst5 ; |G07_28BitAdder|G07_Full_adder:inst37|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst37|inst1 ; |G07_28BitAdder|G07_Full_adder:inst37|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst38|inst5 ; |G07_28BitAdder|G07_Full_adder:inst38|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst38|inst1 ; |G07_28BitAdder|G07_Full_adder:inst38|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst39|inst5 ; |G07_28BitAdder|G07_Full_adder:inst39|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst39|inst1 ; |G07_28BitAdder|G07_Full_adder:inst39|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst40|inst5 ; |G07_28BitAdder|G07_Full_adder:inst40|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst40|inst1 ; |G07_28BitAdder|G07_Full_adder:inst40|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst41|inst5 ; |G07_28BitAdder|G07_Full_adder:inst41|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst41|inst1 ; |G07_28BitAdder|G07_Full_adder:inst41|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst42|inst5 ; |G07_28BitAdder|G07_Full_adder:inst42|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst42|inst1 ; |G07_28BitAdder|G07_Full_adder:inst42|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst43|inst5 ; |G07_28BitAdder|G07_Full_adder:inst43|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst43|inst1 ; |G07_28BitAdder|G07_Full_adder:inst43|inst1 ; out0             ;
+---------------------------------------------+---------------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                                     ;
+---------------------------------------------+---------------------------------------------+------------------+
; Node Name                                   ; Output Port Name                            ; Output Port Type ;
+---------------------------------------------+---------------------------------------------+------------------+
; |G07_28BitAdder|G07_Full_adder:inst18|inst1 ; |G07_28BitAdder|G07_Full_adder:inst18|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst19|inst1 ; |G07_28BitAdder|G07_Full_adder:inst19|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst20|inst1 ; |G07_28BitAdder|G07_Full_adder:inst20|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst21|inst1 ; |G07_28BitAdder|G07_Full_adder:inst21|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst22|inst1 ; |G07_28BitAdder|G07_Full_adder:inst22|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst23|inst1 ; |G07_28BitAdder|G07_Full_adder:inst23|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst24|inst1 ; |G07_28BitAdder|G07_Full_adder:inst24|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst25|inst5 ; |G07_28BitAdder|G07_Full_adder:inst25|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst25|inst1 ; |G07_28BitAdder|G07_Full_adder:inst25|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst26|inst5 ; |G07_28BitAdder|G07_Full_adder:inst26|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst26|inst1 ; |G07_28BitAdder|G07_Full_adder:inst26|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst27|inst5 ; |G07_28BitAdder|G07_Full_adder:inst27|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst27|inst1 ; |G07_28BitAdder|G07_Full_adder:inst27|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst28|inst5 ; |G07_28BitAdder|G07_Full_adder:inst28|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst28|inst1 ; |G07_28BitAdder|G07_Full_adder:inst28|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst29|inst5 ; |G07_28BitAdder|G07_Full_adder:inst29|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst29|inst1 ; |G07_28BitAdder|G07_Full_adder:inst29|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst30|inst5 ; |G07_28BitAdder|G07_Full_adder:inst30|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst30|inst1 ; |G07_28BitAdder|G07_Full_adder:inst30|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst31|inst5 ; |G07_28BitAdder|G07_Full_adder:inst31|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst31|inst1 ; |G07_28BitAdder|G07_Full_adder:inst31|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst32|inst5 ; |G07_28BitAdder|G07_Full_adder:inst32|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst32|inst1 ; |G07_28BitAdder|G07_Full_adder:inst32|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst33|inst5 ; |G07_28BitAdder|G07_Full_adder:inst33|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst33|inst1 ; |G07_28BitAdder|G07_Full_adder:inst33|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst34|inst5 ; |G07_28BitAdder|G07_Full_adder:inst34|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst34|inst1 ; |G07_28BitAdder|G07_Full_adder:inst34|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst35|inst5 ; |G07_28BitAdder|G07_Full_adder:inst35|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst35|inst1 ; |G07_28BitAdder|G07_Full_adder:inst35|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst36|inst5 ; |G07_28BitAdder|G07_Full_adder:inst36|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst36|inst1 ; |G07_28BitAdder|G07_Full_adder:inst36|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst37|inst5 ; |G07_28BitAdder|G07_Full_adder:inst37|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst37|inst1 ; |G07_28BitAdder|G07_Full_adder:inst37|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst38|inst5 ; |G07_28BitAdder|G07_Full_adder:inst38|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst38|inst1 ; |G07_28BitAdder|G07_Full_adder:inst38|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst39|inst5 ; |G07_28BitAdder|G07_Full_adder:inst39|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst39|inst1 ; |G07_28BitAdder|G07_Full_adder:inst39|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst40|inst5 ; |G07_28BitAdder|G07_Full_adder:inst40|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst40|inst1 ; |G07_28BitAdder|G07_Full_adder:inst40|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst41|inst5 ; |G07_28BitAdder|G07_Full_adder:inst41|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst41|inst1 ; |G07_28BitAdder|G07_Full_adder:inst41|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst42|inst5 ; |G07_28BitAdder|G07_Full_adder:inst42|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst42|inst1 ; |G07_28BitAdder|G07_Full_adder:inst42|inst1 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst43|inst5 ; |G07_28BitAdder|G07_Full_adder:inst43|inst5 ; out0             ;
; |G07_28BitAdder|G07_Full_adder:inst43|inst1 ; |G07_28BitAdder|G07_Full_adder:inst43|inst1 ; out0             ;
+---------------------------------------------+---------------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Tue Sep 23 14:06:04 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off G07_Full_adder -c G07_Full_adder
Info: Using vector source file "/28BitFullAdder.vwf"
Info: Overwriting simulation input file with simulation results
    Info: A backup of 28BitFullAdder.vwf called G07_Full_adder.sim_ori.vwf has been created in the db folder
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      79.73 %
Info: Number of transitions in simulation is 4601
Info: Vector file 28BitFullAdder.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 108 megabytes
    Info: Processing ended: Tue Sep 23 14:06:08 2008
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:01


